library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fenpin is
port( clk:in std_logic;
finout:out std_logic);
end fenpin;
architecture bhv of fenpin is
signal tmp:std_logic_vector(3 downto 0);
begin
process(clk)
begin
if clk'event and clk='1' then
if tmp=9 then tmp<="0000";
else tmp<=tmp+1;
end if;
if tmp<5 then finout<='0';
else finout<='1';
end if;
end if;
end process;
end bhv;
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