懂VHDL的高手请进.综合报错.不知怎么解决.

你使用的是运算的重载。所以在程序的起始你要声明库，，
加上
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
问题可以解决。。。。

有些库你没有加进去吧……

以下代码是可以跑的……基本没有改……只是改了下你use部分的~~~

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity eddycoder is
port (a,c:in std_logic; o: out std_logic_vector (3 downto 0));
end eddycoder;

architecture edc of eddycoder is
signal obuff : std_logic_vector (3 downto 0);
BEGIN
process (a,obuff)
BEGIN
if (c = '0') then
obuff<= "0000";
elsif (a'event and a = '1') then
obuff <= obuff+1;
end if;
end process;
o <= obuff;
end edc;