用VHDL语言编写在Quartus II 软件上编译仿真的按键选通模块，U为加键，D为减键，当sel为000时把U给U0、D给

library ieee;
use ieee.std_logic_1164.all;
entity choise is
port ( u,d : in std_logic;
sel: in std_logic_vector(2 downto 0);
u1,u2,u3,u4,u5,u6,d1,d2,d3,d4,d5,d6 : out std_logic);
end entity;
architecture one of choise is
process ( sel ,u,d)
begin
case sel is
when "001" => u1 <= u,d1<=d;
when "010" => u2 <=u,d2<=d;
when "011" => u3 <= u,d3<=d;
when "100" => u4 <=u,d4<=d;
when "101" => u5 <= u,d5<=d;
when "110" => u6 <=u,d6<=d;
when others => null;
end case;
end process;
end architecture;