用VHDL设计一个双进程状态机

VHDL设计一个双进程状态机，原程序如下（后面的图是仿真结果）：

LIBRARY ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity dou_state is

port(clk,rst : in std_logic;

      din    : in std_logic_vector(1 downto 0);

      dout   : out std_logic_vector(3 downto 0));

end dou_state;

architecture arch of dou_state is

type state_type is (s0,s1,s2,s3);

signal state : state_type;

begin

P1: process(clk,rst)

begin

if rst='0' then

state <= s0;

dout  <= "0000";

elsif clk'event and clk='1' then

case state is

when s0 =>

   if din = "10" then

      state <= s1;

   else

      state <= s0;

      dout <= "1001";

   end if;

when s1 =>

   if din = "11" then

      state <= s2;

   else

      state <= s1;

      dout <= "0101";

   end if;

when s2 =>

   if din = "01" then

      state <= s3;

   else

      state <= s2;

      dout <= "1100";

    end if;

when s3 =>

   if din = "00" then

      state <= s0;

   else

      state <= s3;

      dout <= "0010";

   end if;

when others => 

   NULL;

end case;  

end if;

end process;   

end arch;

Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;

ENTITY S is
Port
(
clk : in std_logic;
rst_n : in std_logic;
data_in : in std_logic_vector(1 downto 0);
data_out : out std_logic_vector(3 downto 0)
);
end S;

architecture behav of S is

signal status : std_logic_vector(1 downto 0);

begin
process(clk,rst_n,data_in)
begin
if rst_n = '0' then
data_out <= "0000";
status <= "00";
else if clk'event and clk = '1' then
case status is
when "00" => if data_in = "10" then
status <= "01";
else
status <= "00";
data_out <= "1001";
end if;
when "01" => if data_in = "11" then
status <= "10";
else
status <= "01";
data_out <= "0101";
end if;
when "01" => if data_in = "01" then
status <= "11";
else
status <= "10";
data_out <= "1100";
end if;
when "00" => if data_in = "00" then
status <= "00";
else
status <= "11";
data_out <= "0010";
end if;
when others => status <= "00";
end case;
end if;
end if;
end process;
end behav;