module Verilog1(clk,ldn,k,d,q);
input clk,ldn,k;
input [7:0] d;
output [7:0] q;
reg[7:0] d_reg,q_reg;
always@(negedge ldn)
if(!ldn)
d_reg <= d;
always@(posedge clk )
begin
if(k)
begin//right
q_reg[7:0] <= {1'b00,d_reg[7:1]};
end
else q_reg[7:0] <= {d_reg[6:0],1'b0};
end
assign q = q_reg;
endmodule
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