LIBRARY Ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY count24 IS
PORT(en,clk: IN STD_LOGIC;
co : OUT STD_LOGIC;
clr_l :IN STD_LOGIC; --清零端,低电平有效
d: in STD_LOGIC_VECTOR(3 DOWNTO 0);
ld_l :IN STD_LOGIC; --数据载入控制,低电平有效
qa: out STD_LOGIC_VECTOR(3 DOWNTO 0); --个位数计数
qb: out STD_LOGIC_VECTOR(1 DOWNTO 0)); --十位数计数
END count24;
ARCHITECTURE a1 OF count24 IS
BEGIN --进位控制
process(clk,en)
variable tma: STD_LOGIC_VECTOR(3 DOWNTO 0);
variable tmb: STD_LOGIC_VECTOR(1 DOWNTO 0);
begin
if clk'event and clk='1' then
if clr_l = '0' then tma := (others =>'0'); --同步清0
elsif ld_l ='0' then tma:=d; --置数
elsif en='1' then
if tma="1001" then tma:="0000";tmb:=tmb+1;
Elsif tmb="10" and tma="0011" then tma:="0000";
tmb:="00";co<='1';
else tma:=tma+1;co<='0';
end if;
end if;
end if;
qa<=tma;
qb<=tmb;
end process;
END a1;