求高手帮忙做个EDA技术的VHDL编程题。谢谢 设计一个含异步复位和计数使能的11位二进制加减可控的计数器。

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY DECODE3_8 IS
PORT ( DIN : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
EN : IN STD_LOGIC;
XOUT : OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
END DECODE3_8;
ARCHITECTURE ONE OF DECODE3_8 IS
BEGIN
PROCESS (DIN, EN)
BEGIN
IF EN = ‘1’ THEN
IF DIN = “111” THEN XOUT <= “11111110”;
ELSIF DIN = “110” THEN XOUT <= “11111101”;
ELSIF DIN = “101” THEN XOUT <= “11111011”;
ELSIF DIN = “100” THEN XOUT <= “11110111”;
ELSIF DIN = “011” THEN XOUT <= “11101111”;
ELSIF DIN = “010” THEN XOUT <= “11011111”;
ELSIF DIN = “001” THEN XOUT <= “10111111”;
ELSE XOUT <= “11111011”;
END IF;
END PROCESS;
END ONE;

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