谁能提供：用Verilog HDl 语言编写：能显示时，分，秒的数字时钟，同时能在6个共阳极管上显示，可实异步清

module display(clk,reset,seg_r,dig_r);
input clk;
input reset;
output[7:0] seg_r;
output[7:0] dig_r;
reg[25:0] count;
reg[15:0] hour;
reg sec;
reg[4:0] disp_dat;
reg[7:0] seg_r;
reg[7:0] dig_r;
always @(posedge clk) //定义clock上升沿触发
begin
count = count + 1'b1;
if(count == 26'd24000000) //0.5S到了吗？
begin
count = 25'd0; //计数器清零
sec = ~sec; //置位秒标志
end
end

always @(negedge sec) //计时处理
begin
if(reset==0)
hour[15:0]=0;
else
begin
hour[3:0] = hour[3:0]+1'b1; //秒加1
if(hour[3:0] == 4'ha)
begin
hour[3:0] = 4'h0;
hour[7:4] = hour[7:4]+1'b1; //秒的十位加一
if(hour[7:4] == 4'h6)
begin
hour[7:4] = 4'h0;
hour[11:8] = hour[11:8] + 1'b1; //分个位加一
if(hour[11:8] ==4'ha)
begin
hour[11:8] = 4'h0;
hour[15:12] = hour[15:12] + 1'b1; //分十位加一
if(hour[15:12] == 4'h6)
hour[15:12] =4'h0;
end
end
end
end
end
always @(posedge clk) //count[17:15]大约1ms改变一次
begin
case(count[17:15]) //选择扫描显示数据
3'd0:disp_dat = hour[3:0]; //秒个位
3'd1:disp_dat = hour[7:4]; //秒十位
3'd2:disp_dat = 4'ha; //显示"-"
3'd3:disp_dat = hour[11:8]; //分个位
3'd4:disp_dat = hour[15:12]; //分十位
3'd5:disp_dat = 4'ha; //显示"-"
3'd6:disp_dat = 4'h0; //时个位，本次实验不计小时
3'd7:disp_dat = 4'h0; //时十位，本次实验不计小时
endcase
case(count[17:15]) //选择数码管显示位
3'd0:dig_r = 8'b11111110; //选择第一个数码管显示
3'd1:dig_r = 8'b11111101; //选择第二个数码管显示
3'd2:dig_r = 8'b11111011; //选择第三个数码管显示
3'd3:dig_r = 8'b11110111; //选择第四个数码管显示
3'd4:dig_r = 8'b11101111; //选择第五个数码管显示
3'd5:dig_r = 8'b11011111; //不显示
3'd6:dig_r = 8'b11111111; //不显示
3'd7:dig_r = 8'b11111111; //不显示
endcase
end
always @(posedge clk)
begin
case(disp_dat)
4'h0:seg_r = 8'hc0; //显示0
4'h1:seg_r = 8'hf9; //显示1
4'h2:seg_r = 8'ha4; //显示2
4'h3:seg_r = 8'hb0; //显示3
4'h4:seg_r = 8'h99; //显示4
4'h5:seg_r = 8'h92; //显示5
4'h6:seg_r = 8'h82; //显示6
4'h7:seg_r = 8'hf8; //显示7
4'h8:seg_r = 8'h80; //显示8
4'h9:seg_r = 8'h90; //显示9
4'ha:seg_r = 8'hbf; //显示-
default:seg_r = 8'hff; //不显示
endcase
if((count[17:15]== 3'd2)&sec)
seg_r = 8'hff;
if((count[17:15]== 3'd5)&sec)
seg_r = 8'hff;
end
endmodule