一位全加器源代码如下：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity bit1adder is
port(
a,b,ci:in std_logic;
s,co:out std_logic
);
end bit1adder;
architecture func of bit1adder is
signal:x,y:std_logic;
begin
x<=a xor b;
y<=x and ci;
s<=x xor ci;
co<=y or (a and b);
end func;
内容全部来源于网络收集，如有侵权，请联系网站删除：QQ：24596024