library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fp is
port(clk: in std_logic;
fpclk: out std_logic);
end fp;
architecture arc of fp is
begin
process(clk)
variable count: integer range 0 to 24;
variable clk0: std_logic;
begin
if clk'event and clk='1' then
if count=24 then
clk0:=not clk0;
count:=0;
else
count:=count+1;
end if;
end if;
fpclk<=clk0;
end process;
end arc;
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