请问怎么样用VHDL设计一个倒计时计数器

这个程序主要是分频器的用法吧！给你个程序，希望是你想要的
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY FFF IS
PORT(CLK,RESET:IN STD_LOGIC; ---系统时钟和复位信号
LOAD:IN STD_LOGIC; ---实现将你要预置的数输入给计数器
CURRENT:IN INTEGER RANGE 0 TO 10000;--你要预置的数
COUNT:OUT INTEGER RANGE 0 TO 10000;--计数器计数值
FENMIN:OUT STD_LOGIC); ---蜂鸣器值
END;
ARCHITECTURE ART OF FFF IS
SIGNAL COUNT_1,COUNT_2,COUNT_D:INTEGER RANGE 0 TO 10000;
SIGNAL CLK_1,CLK_2:STD_LOGIC;
BEGIN
PROCESS(CLK,RESET) ----编写1hz时钟
BEGIN
IF RESET='1' THEN
COUNT_1<=0;
ELSIF CLK'EVENT AND CLK='1' THEN
IF COUNT_1=500 THEN
COUNT_1<=0;
CLK_1<=NOT CLK_1;
ELSE COUNT_1<=COUNT_1+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLK,RESET) ---编写50hz的时钟
BEGIN
IF RESET='1' THEN
COUNT_2<=0;
ELSIF CLK'EVENT AND CLK='1' THEN
IF COUNT_2=100 THEN
COUNT_2<=0;CLK_2<=NOT CLK_2;
ELSE COUNT_2<=COUNT_2+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLK_1,CLK_2,LOAD,CURRENT,RESET)---实现计数器自减
BEGIN
IF RESET='1' THEN
COUNT_D<=0;
ELSIF LOAD='1' THEN
COUNT_D<=CURRENT;
ELSIF CLK_1'EVENT AND CLK_1='1' THEN
IF COUNT_D=0 THEN
COUNT_D<=0;
ELSE COUNT_D<=COUNT_D-1;
END IF;
END IF;
COUNT<=COUNT_D;
END PROCESS;
PROCESS(COUNT_D) ---当计数值为0时，蜂鸣器响
BEGIN
IF COUNT_D=0 THEN
FENMIN<=CLK_2;
ELSE FENMIN<='0';
END IF;
END PROCESS;
END ART;