vhdl 如何调用子模块

写了个简单的例子，基本上就是这样，建议还是去看看VHDL的语法。
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity simtop is
end simtop;

architecture beheav of simtop is
signal S_CLK : std_logic;
signal S_RSTN : std_logic;
signal S_DIN : std_logic := '1';
signal S_DOUT : std_logic;

component CLK_GEN
port( RSTN : out std_logic;
CLK : out std_logic);
end component ;
component submode
port( RSTN :in std_logic;
CLK :in std_logic;
DIN :in std_logic;
DOUT :out std_logic);
end component ;

begin
CLK_GEN_INST : CLK_GEN
port map(RSTN => S_RSTN,
CLK => S_CLK
);
submode_inst : submode
port map(
RSTN =>S_RSTN,
CLK =>S_CLK ,
DIN =>S_DIN ,
DOUT =>S_DOUT
);
end beheav;