用VHDL语言编写七段显示译码器，输入端口D输入0~9二进制数，译出的数码管显示码由X端口输出

共阴极数码管：
library ieee;
use ieee.std_logic_1164.all;

entity seven_seg is
port(
D :in std_logic_vector(3 downto 0); --4 bits latch input
X :out std_logic_vector(6 downto 0); --to seven segment
);
end seven_seg;
architecture arch_seven_seg of seven_seg is
begin
process(D)
begin
case D is
when "0000"=> X <="1111110"; --0 number to show
when "0001"=> X <="0110000"; --1
when "0010"=> X <="1101101"; --2
when "0011"=> X <="1111001"; --3
when "0100"=> X <="0110011"; --4
when "0101"=> X <="1011011"; --5
when "0110"=> X <="1011111"; --6
when "0111"=> X <="1110000"; --7
when "1000"=> X <="1111111"; --8
when "1001"=> X <="1111011"; --9
when OTHERS=> X <=(OTHERS => '0');
end case;
end process;
end arch_seven_seg;

VHDL的吗？我这有共阳极的。