verilog中多个module怎么定义实体名称?

2024-12-18 20:03:18
推荐回答(2个)
回答1:

module ASRAM(port definition);

io declaration;

endmodule

ASRAM_1 ASRAM_2 ASRAM_3 ASRAM_4
实例化该ASRAM

ASRAM ASRAM_1(
.port(instant_port),
.port_2(instant_port_2)

);

回答2:

没有这个module,
module ASRAM;
//body
endmodule