用vhdl设计4位同步二进制加法计数器，输入为时钟端clk和异步清除端clr，进位输出端为c

library ieee;
use ieee.std_logic_1164.all;

entity cnt4e is
port(
clk,clr:in std_logic;
c:out std_logic;
q:buffer integer range 0 to 15);
end cnt4e;

architecture one of cnt4e is
begin

process(clk,clr)
begin
if clr = '1' then --异步清零
q<=0;c<='0';
elsif clk'event and clk='1'then --同步加计数
if q=15 then
q<=0;c<='0';
elsif q=14 then --带进位输出
q<=q+1;c<='1';
else
q<=q+1;
end if;
end if;
end if;
end process;

end one;

对，差不多 还定居的v你的是div军事divu