如何用VHDL语言编程基本RS触发器……

根据真值表的描述结合VHDL编程思想很好实现你想要的程序；
程序并不难，关键是你用心的程度；
我猜你也许也是一名我的同行……
自己的努力才是过硬的本领！！！！
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RS_clk IS
PORT( S,R,res :IN std_logic;
Q,NOT_Q:out std_logic);
END RS_clk;
ARCHITECTURE behav OF RS_clk IS
signal sel1,sel2: std_logic;
BEGIN
process(res,sel1,sel2)
begin
if res='0' then sel1<='0';
sel2<='1';
elsif (S='1' and R='0') then sel1<='1';
sel2<='0';
elsif (S='0' and R='1') then sel1<='0';
sel2<='1';
elsif (S='0' and R='0') then sel1<=sel1;
sel2<=sel2;
end if;
Q<=sel1;
NOT_Q<=sel2;
end process;
END behav;

重新给你写了一个：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY RS_clk IS
PORT( S,R,res :IN std_logic;
Q,NOT_Q:out std_logic);
END RS_clk;
ARCHITECTURE behav OF RS_clk IS
signal sel1,sel2: std_logic;

BEGIN
process(res,sel1,sel2)
begin
if res='0' then sel1<='0';
sel2<='1';
elsif (S='1' and R='0') then sel1<='1';
sel2<='0';
elsif (S='0' and R='1') then sel1<='0';
sel2<='1';
elsif (S='0' and R='0') then sel1<=sel1;
sel2<=sel2;
end if;
Q<=sel1;
NOT_Q<=sel2;
end process;
END behav;

library ieee;
use ieee.std_logic_1164.all;

entity sync_rsdff is
port(d,clk : in std_logic;
set : in std_logic;
reset: in std_logic;
q,qb : out std_logic);
end sync_rsdff;

architecture rtl_arc of sync_rsdff is
process(clk)
begin
if (clk'event and clk='1') then
if(set='0' and reset='1') then
q<='1';
qb<='0';
elsif (set='1' and reset='0') then
q<='0';
qb<='1';
else
q<=d;
qb<=not d;
end if;
end process;
end rtl_arc;