EDA课程设计五进制计数器的VHDL语言设计的源程序

　　随便编了一个，能通过仿真。
　　library ieee;
　　use ieee.std_logic_1164.all;
　　use ieee.std_logic_unsigned.all;

　　entity cnt5 is
　　port(clk,rst:in std_logic;
　　SEL:in std_logic_vector(1 downto 0);
　　data1_out,data2_out,data3_out:out std_logic_vector(6 downto 0));
　　end cnt5;

　　architecture arch of cnt5 is

　　signal count:integer range 0 to 9;
　　signal state:std_logic_vector(1 downto 0);
　　begin
　　process(clk,rst)
　　begin
　　if rst='1' then
　　state<="00";data1_out<="1111110";data2_out<="1111110";data3_out<="1111110";count<=0;
　　elsif clk'event and clk='1' then
　　case state is
　　when "00" =>
　　data1_out<="1111110";data2_out<="1111110";
　　if count=4 then count<=0; else count<=count+1;end if;
　　case SEL is
　　when "01" => state<="01";count<=0;
　　when "10" => state<="10";count<=1;
　　when "11" => state<="11";count<=5;
　　when others => null;
　　end case;
　　when "01" =>
　　data1_out<="1111110";data2_out<="0110000";
　　if count=8 then count<=0; else count<=count+2;end if;
　　case SEL is
　　when "00" => state<="00";count<=0;
　　when "10" => state<="10";count<=1;
　　when "11" => state<="11";count<=5;
　　when others => null;
　　end case;
　　when "10" =>
　　data1_out<="0110000";data2_out<="1111110";
　　if count=9 then count<=1; else count<=count+2;end if;
　　case SEL is
　　when "00" => state<="00";count<=0;
　　when "01" => state<="01";count<=0;
　　when "11" => state<="11";count<=5;
　　when others => null;
　　end case;
　　when "11" =>
　　data1_out<="0110000";data2_out<="0110000";
　　if count=1 then count<=5; else count<=count-1;end if;
　　case SEL is
　　when "00" => state<="00";count<=0;
　　when "01" => state<="01";count<=0;
　　when "10" => state<="10";count<=1;
　　when others => null;
　　end case;
　　when others => state <= "00";
　　end case;

　　case count is
　　when 0 => data3_out<="1111110";
　　when 1 => data3_out<="0110000";
　　when 2 => data3_out<="1101101";
　　when 3 => data3_out<="1111001";
　　when 4 => data3_out<="0110011";
　　when 5 => data3_out<="1011011";
　　when 6 => data3_out<="1011111";
　　when 7 => data3_out<="1110000";
　　when 8 => data3_out<="1111111";
　　when 9 => data3_out<="1111011";
　　when others => data3_out<="0000000";
　　end case;

　　end if;
　　end process;
　　end arch;

随便编了一个，能通过仿真。
library
ieee;
use
ieee.std_logic_1164.all;
use
ieee.std_logic_unsigned.all;
entity
cnt5
is
port(clk,rst:in
std_logic;
SEL:in
std_logic_vector(1
downto
0);
data1_out,data2_out,data3_out:out
std_logic_vector(6
downto
0));
end
cnt5;
architecture
arch
of
cnt5
is
signal
count:integer
range
0
to
9;
signal
state:std_logic_vector(1
downto
0);
begin
process(clk,rst)
begin
if
rst='1'
then
state<="00";data1_out<="1111110";data2_out<="1111110";data3_out<="1111110";count<=0;
elsif
clk'event
and
clk='1'
then
case
state
is
when
"00"
=>
data1_out<="1111110";data2_out<="1111110";
if
count=4
then
count<=0;
else
count<=count+1;end
if;
case
SEL
is
when
"01"
=>
state<="01";count<=0;
when
"10"
=>
state<="10";count<=1;
when
"11"
=>
state<="11";count<=5;
when
others
=>
null;
end
case;
when
"01"
=>
data1_out<="1111110";data2_out<="0110000";
if
count=8
then
count<=0;
else
count<=count+2;end
if;
case
SEL
is
when
"00"
=>
state<="00";count<=0;
when
"10"
=>
state<="10";count<=1;
when
"11"
=>
state<="11";count<=5;
when
others
=>
null;
end
case;
when
"10"
=>
data1_out<="0110000";data2_out<="1111110";
if
count=9
then
count<=1;
else
count<=count+2;end
if;
case
SEL
is
when
"00"
=>
state<="00";count<=0;
when
"01"
=>
state<="01";count<=0;
when
"11"
=>
state<="11";count<=5;
when
others
=>
null;
end
case;
when
"11"
=>
data1_out<="0110000";data2_out<="0110000";
if
count=1
then
count<=5;
else
count<=count-1;end
if;
case
SEL
is
when
"00"
=>
state<="00";count<=0;
when
"01"
=>
state<="01";count<=0;
when
"10"
=>
state<="10";count<=1;
when
others
=>
null;
end
case;
when
others
=>
state
<=
"00";
end
case;
case
count
is
when
0
=>
data3_out<="1111110";
when
1
=>
data3_out<="0110000";
when
2
=>
data3_out<="1101101";
when
3
=>
data3_out<="1111001";
when
4
=>
data3_out<="0110011";
when
5
=>
data3_out<="1011011";
when
6
=>
data3_out<="1011111";
when
7
=>
data3_out<="1110000";
when
8
=>
data3_out<="1111111";
when
9
=>
data3_out<="1111011";
when
others
=>
data3_out<="0000000";
end
case;
end
if;
end
process;
end
arch;

呵呵，我也想要这个，一模一样的