verilog语言 数码管显示十进制数

闲来无事，做做看。
module xue3(iSW,oHEX3,oHEX2,oHEX1,oHEX0);
input [3:0] iSW;
output oHEX3,oHEX2,oHEX1,oHEX0;
//下面点亮四个七段数码管
bcd7seg digit0(iSW[3:0],oHEX0);
bcd7seg digit1(iSW[3:0],oHEX1);
bcd7seg digit2(iSW[3:0],oHEX2);
bcd7seg digit3(iSW[3:0],oHEX3);
endmodule
//下面是子模块。欢~~迎~~加fpga~qun~~37378637 /////////////
module bcd7seg(B,H);
input [3:0] B;
output reg H;
always @(B) begin
case (B) //选择输出数据，这里采用的是共阳极接法,要是共阴极各数按位全部取反即可。从最低位开始分别代表了七段中的abcdefg第8位是D.P段
4'h0: H = 8'hc0; //显示0
4'h1: H = 8'hf9; //显示1
4'h2: H = 8'ha4; //显示2
4'h3: H = 8'hb0; //显示3
4'h4: H = 8'h99; //显示4
4'h5: H = 8'h92; //显示5
4'h6: H = 8'h82; //显示6
4'h7: H = 8'hf8; //显示7
4'h8: H = 8'h80; //显示8
4'h9: H = 8'h90; //显示9
4'ha: H = 8'h88; //显示a
4'hb: H = 8'h83; //显示b
4'hc: H = 8'hc6; //显示c
4'hd: H = 8'ha1; //显示d
4'he: H = 8'h86; //显示e
4'hf: H = 8'h8e; //显示f
default: H =8'hff; //全灭
endcase
end
endmodule

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