用VHDL编程：异步清零的D触发器

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity DFF_ASY is
port (
CLOCK : in std_logic ;--clock
RESET : in std_logic ;--reset
DFF_IN : in std_logic ;--data in
DFF_OUT : out std_logic --data out
);
end DFF_ASY;

architecture RTL of DFF_ASY is

signal REG_DFF_OUT : std_logic ; -- internal signals

begin

process (CLOCK,RESET) begin
if (RESET = '1') then -- asynchronous reset
REG_DFF_OUT <= '0';
elsif (CLOCK'event and CLOCK = '1') then
REG_DFF_OUT <= DFF_IN ;
end if;
end process;

DFF_OUT <= REG_DFF_OUT ;

end RTL;

下面是同步清零的例子:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity DFF_SYN is
port (
CLOCK : in std_logic ;--clock
RESET : in std_logic ;--reset
DFF_IN : in std_logic ;--data in
DFF_OUT : out std_logic --data out
);
end DFF_SYN;

architecture RTL of DFF_SYN is

signal REG_DFF_OUT : std_logic ; -- internal signals

begin

process (CLOCK) begin
if (CLOCK'event and CLOCK = '1') then
if (RESET) then
REG_DFF_OUT <= '0' ;
else
REG_DFF_OUT <= DFF_IN ;
end if ;
end if;
end process;

DFF_OUT <= REG_DFF_OUT ;

end RTL;

好容易挣的分啊，直接装一个软件ISE/QUARTUS,模板里都有。

library
IEEE;
use
IEEE.std_logic_1164.all;
use
IEEE.std_logic_unsigned.all;
entity
DFF_ASY
is
port
(
CLOCK
:
in
std_logic
;--clock
RESET
:
in
std_logic
;--reset
DFF_IN
:
in
std_logic
;--data
in
DFF_OUT
:
out
std_logic
--data
out
);
end
DFF_ASY;
architecture
RTL
of
DFF_ASY
is
signal
REG_DFF_OUT
:
std_logic
;
--
internal
signals
begin
process
(CLOCK,RESET)
begin
if
(RESET
=
'1')
then
--
asynchronous
reset
REG_DFF_OUT
<=
'0';
elsif
(CLOCK'event
and
CLOCK
=
'1')
then
REG_DFF_OUT
<=
DFF_IN
;
end
if;
end
process;
DFF_OUT
<=
REG_DFF_OUT
;
end
RTL;
下面是同步清零的例子:
library
IEEE;
use
IEEE.std_logic_1164.all;
use
IEEE.std_logic_unsigned.all;
entity
DFF_SYN
is
port
(
CLOCK
:
in
std_logic
;--clock
RESET
:
in
std_logic
;--reset
DFF_IN
:
in
std_logic
;--data
in
DFF_OUT
:
out
std_logic
--data
out
);
end
DFF_SYN;
architecture
RTL
of
DFF_SYN
is
signal
REG_DFF_OUT
:
std_logic
;
--
internal
signals
begin
process
(CLOCK)
begin
if
(CLOCK'event
and
CLOCK
=
'1')
then
if
(RESET)
then
REG_DFF_OUT
<=
'0'
;
else
REG_DFF_OUT
<=
DFF_IN
;
end
if
;
end
if;
end
process;
DFF_OUT
<=
REG_DFF_OUT
;
end
RTL;

给你个连接看看
http://jpkc.hdu.edu.cn/computer/zcyl//upload/GAL%E4%B8%AD%E5%BC%82%E6%AD%A5%E6%B8%85%E9%9B%B6D%E8%A7%A6%E5%8F%91%E5%99%A8%E7%9A%84%E5%AE%9E%E7%8E%B0%E6%96%B9%E6%B3%95%E5%8F%8A%E5%BA%94%E7%94%A8.pdf