Error (10170): Verilog HDL syntax error at Verilog1.v(2) near text "74138"; expecting an identifier

/*TTL module 74138*/
module a74138(Y,A,G1,G2);
output[7:0]Y;
input[2:0]A;
input G1,G2;
reg[7:0]Y;
wire G;
assign G=G1&~G2;
always@(A or G1 or G2)
begin
if(G)
case(A)
3'd0:Y=8'b11111110;
3'd1:Y=8'b11111101;
3'd2:Y=8'b11111011;
3'd3:Y=8'b11110111;
3'd4:Y=8'b11101111;
3'd5:Y=8'b11011111;
3'd6:Y=8'b10111111;
3'd7:Y=8'b01111111;
endcase
else
Y=8'b11111111;
end
endmodule

module exam3(D8,D7,D6,K8,K7,K6);
output D8,D7,D6;
input K8,K7,K6;
wire[7:0]Y;
wire[2:0]A;
wire VCC,GND;
assign A[2]=K8;
assign A[1]=K7;
assign A[0]=K6;
assign VCC=1;
assign GND=0;
//module 138(Y,A,G1,G2);
a74138 u1(.Y(Y),.A(A),.G1(VCC),.G2(GND));
nand u2(D8,Y[6],Y[5],Y[4],Y[3]);
nand u3(D7,Y[3],Y[3],Y[1]);
nand u4(D6,Y[5],Y[3],Y[2]);
endmodule
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模块名不能为纯数字组合+若干低级错误
我改过编译通过了，你自己对照着看吧
望及时采纳！！

74138u1(.Y(Y),.A(A),.G1(VCC),.G2(GND));
74138和u1之间加个空格试试

一个文件里有两个模块？