用VHDL语言描述4位二进制数据比较器

2025-01-01 21:54:16
推荐回答(1个)
回答1:

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY COMPARE IS
GENERIC(SIZE:INTEGER:=4);
PORT (DAT1,DAT2:IN STD_LOGIC_VECTOR(SIZE DOWNTO 1);
MAX:OUT STD_LOGIC_VECTOR(SIZE DOWNTO 1));
END ENTITY COMPARE;
ARCHITECTURE ART OF COMPARE IS
BEGIN
PROCESS(DAT1,DAT2)
BEGIN
IF(DAT1(SIZE-1 DOWNTO 1)>DAT2(SIZE-1 DOWNTO 1)) THEN
MAX<=DAT1;
ELSE MAX<=DAT2;
END IF;
END PROCESS;
END ARCHITECTURE ART;
里面的长度可以改