用verilog语言编的简单的交通灯控制系统 怎样把内部的倒计时显示出来

//绿灯亮40秒，转黄灯；
//黄灯亮5秒，转左转灯；
//左转灯亮15秒，转黄灯；
//黄灯亮5秒，转红灯；
//红灯亮55秒，转绿灯；

//lamp从高到低 分别接红灯 黄灯 绿灯 左转灯
//account接2个数码管

module traffic(clk,en,lamp,acount);
output[7:0] acount;
output[3:0] lamp;
input clk,en;

reg[7:0] num;
reg temp;
reg[2:0] count;
reg[7:0] red,yellow,green,left;
reg[3:0] lamp;

always @(en)
if(!en)
begin
red<=8'd55; //55 second
yellow<=8'd5;
green<=8'd40;
left<=8'd15;
end

assign acount=num;

always @(posedge clk)
begin
if(en)
begin
if(!temp)
begin
temp<=1;
case(count)
0:begin num<=green;lamp<=2;count<=1; end //green
1:begin num<=yellow;lamp<=4;count<=2;end //yellow
2:begin num<=left;lamp<=1;count<=3;end //left
3:begin num<=yellow;lamp<=4;count<=4;end //yellow
4:begin num<=red; lamp<=8;count<=0;end //red
default:lamp<=8;
endcase
end
else
begin
if(num>1)
if(num[3:0]==0)
begin
num[3:0]<=4'b1001;
num[7:4]<=num[7:4]-1;
end
else
num[3:0]<=num[3:0]-1;
if(num==2) temp<=0;
end
end
else
begin
lamp<=4'b1000;
count<=0;
temp<=0;
end
end

endmodule