Error (10171): Verilog HDL syntax error at ps2_mouse_test.v(88) near end of file ; expecting ".",

2024-12-25 15:06:32
推荐回答(1个)
回答1:

Endmodule这里错了啊
verilog是严格区分大小写的
所以编译器不认识Endmodule
只需要改成endmodule就OK了啊~