分频器采用VHDL文本输入方式设计，将1MHz的时钟输入信号（clk）分频为1Hz的输出信号（clkfp）。

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity div is
generic(n:integer :=1000000);
port (clk:in std_logic;
q:out std_logic);
end div;
architecture behave of div is
signal count :integer range n-1 downto 0:=n-1;
begin
process(clk)
begin
if rising_edge(clk) then
count<=count-1;
if count>=n/2 then
q<='0';
else
q<='1';
end if;
if count<=0 then
count<=n-1;
end if;
end if;
end process;
end behave;

我手上恰好有这样的一份文档，