用Verilog实现50MHz分频为8Hz的程序怎么写?

2024-12-29 23:53:07
推荐回答(1个)
回答1:

50M分频道8hz的话 50 000 000/8=6250000
reg clk_div8;
reg [23:0]cnt;
always @(posedge clk)
begin
if(!rst_n)

begin

clk_div8<=0;
cnt<=0;

end
else if(cnt==24'd3125000)
begin

cnt<=0;
clk_div8<=~clk_div8;
end
end

分析:50M周围为20ns,在3125000*20ns=0.0625s后clk_div8翻转,即clk_div8周期为2*0.0625s=0.125s,然后就是8hz了,可以追问,望采纳