如何用VHDL语言使32768晶振分频出1HZ的信号时钟

下面这个是我自己写的，你修改下就可以了，占空比是50%的
怎么修改呢，generic(n:integer:=10); 改成generic(n:integer:=32768);就可以了，下面是程序：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity div1hz is
generic(n:integer:=10);
port(clk:in std_logic;
clock:out std_logic);
end;
architecture a of div1hz is
signal count:integer range 0 to n;
signal mid:std_logic;
begin
process(clk)
begin
if clk'event and clk='1' then
count<=count+1;
if count=n-1 then
count<=0;
else
if count clock<='0';
else clock<='1';
end if;
end if;
end if;
end process;
end;

还有这个，不过占空比是1/32768了，是百度知道一个人的回答的
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity fenpin is
port(
clk_in : in std_logic;
clk_out : out std_logic
);
end fenpin;

architecture structure of fenpin is

signal count:integer range 0 to 32767:=0;

begin

process(clk_in)
begin
if(clk_in'event and clk_in='1')then
if( count = 32767 )then
clk_out <= '1';
count <= 0;
else
count <= count + 1;
clk_out <= '0';
end if;
end if;
end process;
end structure;

就是要编一个分频器吧，，，我不知道32768晶振频率是多大，我就以把频率为1MHz的分频出1Hz为例给你参考参考 吧
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fenpin is
port(clk:in std_logic;
clock:out std_logic)j;
end;
architecture art of fenpin is
signal count:integer range 0 to 500000;
signal clk_data:std_logic;
begin
process(clk)
begin
if clk'event and clk='1' then
if count=500000 then -------频率多大，你可以改这个 计算公式为
count<=0; f1=2*count*f2,f1为分频前的频率
clk_data<=not clk_data; f2为分频后的频率
else count<=count_1;
end if;
end if;
clock<=clk_data;
end process;
end art;