有懂VHDL硬件描述语言的吗？用这个语言编程的？

书上六大页的程序，谁为了0分给你抄！

我来补充回答了，添加如下内容：
LIBRARY IEEE ;
USE IEEE.std_logic_1164.ALL ;
USE IEEE.std_logic_unsigned.ALL ;
entity CH41A is --选择开关
port ( sel: in std_logic_vector(2 downto 0);
d0,d1,d2,d3,d4,d5: in std_logic_vector(7 downto 0);
q: out std_logic_vector( 7 downto 0));
end CH41A;
architecture CH41_arc of CH41A is
begin
process(SEL)
begin
case sel is
when"000" =>q<=d0;
when"001" =>q<=d1;
when"010" =>q<=d2;
when"011" =>q<=d3;
when"100" =>q<=d4;
when"101" =>q<=d5;
when others=>null;
end case;
end process;
end ch41_arc;
LIBRARY IEEE ;
USE IEEE.std_logic_1164.ALL ;
USE IEEE.std_logic_unsigned.ALL ;
entity JIAN is --递减模块
port (clk,reset : in std_logic ;
q: out std_logic_vector(7 downto 0));
END JIAN;
architecture JIAN_arc of JIAN is
begin
process(clk,reset)
variable tmp: std_logic_vector(7 downto 0);
begin
if reset='0' then
tmp:= "11111111";
elsif clk'event and clk = '1' then
if tmp="00000000" then
tmp:= "11111111";
else
tmp:=tmp-1;
end if ;
end if ;
q<=tmp;
end process ;
end JIAN_arc;
LIBRARY IEEE ; ---阶梯模块
USE IEEE.std_logic_1164.ALL ;
USE IEEE.std_logic_unsigned.ALL ;
entity LADDER is
port (clk,reset: in std_logic ;
q: out std_logic_vector(7 downto 0));
end LADDER;
architecture LADDER_arc of LADDER is
begin
process(clk,reset)
variable tmp: std_logic_vector(7 downto 0);
variable a:std_logic;
begin
if reset='0' then
tmp:= "00000000";
elsif clk'event and clk = '1' then
if a='0'then
if tmp="11111111" then
tmp:= "00000000";
a:='1';
else
tmp:=tmp+16;
a:='1';
end if ;
else
a:='0';
end if ;
end if ;
q<=tmp;
end process ;
end LADDER_arc;
LIBRARY IEEE ;
USE IEEE.std_logic_1164.ALL ;
USE IEEE.std_logic_unsigned.ALL ;
entity SQUARE is --方波模块
port (clk,clr: in std_logic ;
q: out integer range 0 to 255);
end SQUARE;
architecture SQUARE_arc of SQUARE is
signal a: BIT;
begin
process(clk,clr)
variable cnt: integer range 0 to 63;
begin
if clr='0' then
a<='0';
elsif clk'event and clk = '1' then
if cnt<63 then
cnt:=cnt+1;
else
cnt:=0;
a<=not a;
end if;
end if;
end process ;
process(clk,a)
begin
if clk'event and clk = '1' then
if a='1' then
q<=255;
else
q<=0;
end if;
end if;
end process ;
end SQUARE_arc;

LIBRARY IEEE ;
USE IEEE.std_logic_1164.ALL ;
USE IEEE.std_logic_unsigned.ALL ;
entity zeng is --递增模块
port (clk,reset : in std_logic ;
q: out std_logic_vector(7 downto 0));
end zeng;
architecture zeng_arc of zeng is
begin
process(clk,reset)
variable tmp: std_logic_vector(7 downto 0);
begin
if reset='0' then
tmp:= "00000000";
elsif clk'event and clk='1' then
if tmp="11111111" then
tmp:= "00000000";
else
tmp:=tmp+1;
end if ;
end if ;
q<=tmp;
end process ;
end zeng_arc;
LIBRARY IEEE ;
USE IEEE.std_logic_1164.ALL ;
USE IEEE.std_logic_unsigned.ALL ;
entity DELTA is --三角波模块
port (clk,reset : in std_logic ;
q: out std_logic_vector(7 downto 0));
end DELTA;
architecture DELTA_arc of DELTA is
begin
process(clk,reset)
variable tmp: std_logic_vector(7 downto 0);
variable a: std_logic;
begin
if reset='0' then
tmp:= "00000000";
elsif clk'event and clk = '1' then
if a='0'then
if tmp="11111110" then
tmp:= "11111111";
a:='1';
else
tmp:=tmp+1;
end if ;
else
if tmp="00000001"then
tmp:="00000000";
a:='0';
else
tmp:=tmp-1;
end if ;
end if ;
end if ;
q<=tmp;
end process ;
end DELTA_arc;

LIBRARY IEEE ;
USE IEEE.std_logic_1164.ALL ;
USE IEEE.std_logic_unsigned.ALL ;
entity SIN is --正弦波模块
port (clk,clr: in std_logic ;
d: out integer range 0 to 255);
end SIN;
architecture SIN_arc of SIN is
begin
process(clk,clr)
variable tmp: integer range 0 to 63;
begin
if clr='0' then
d<=0;
elsif clk'event and clk = '1' then
if tmp=63 then
tmp:=0;
else
tmp:=tmp+1;
end if;
case tmp is
when 00=>d<=255; when 01=>d<=254; when 02=>d<=252;
when 03=>d<=249; when 04=>d<=245; when 05=>d<=239;
when 06=>d<=233; when 07=>d<=225; when 08=>d<=217;
when 09=>d<=207; when 10=>d<=197; when 11=>d<=186;
when 12=>d<=174; when 13=>d<=162; when 14=>d<=150;
when 15=>d<=137; when 16=>d<=124; when 17=>d<=112;
when 18=>d<=99; when 19=>d<=87; when 20=>d<=75;
when 21=>d<=64; when 22=>d<=53; when 23=>D<=43;
when 24=>d<=34; when 25=>d<=26; when 26=>d<=19;
when 27=>d<=13; when 28=>d<=8; when 29=>d<=4;
when 30=>d<=1; when 31=>d<=0; when 32=>d<=0;
when 33=>d<=1; when 34=>d<=4; when 35=>d<=8;
when 36=>d<=13; when 37=>d<=19; when 38=>d<=26;
when 39=>d<=34; when 40=>d<=43; when 41=>d<=53;
when 42=>d<=64; when 43=>d<=75; when 44=>d<=87;
when 45=>d<=99; when 46=>d<=112; when 47=>d<=124;
when 48=>d<=137; when 49=>d<=150; when 50=>d<=162;
when 51=>d<=174; when 52=>d<=186; when 53=>d<=197;
when 54=>d<=207; when 55=>d<=217; when 56=>d<=225;
when 57=>d<=233; when 58=>d<=239; when 59=>d<=245;
when 60=>d<=249; when 61=>d<=252; when 62=>d<=254;
when 63=>d<=255; when others=>null;
end case;
end if;
end process;end sin_arc;