vhdl 数据选择器设计8选1 用CASE语句

module mux8_1(DOUT,A,D0,D1,D2,D3,D4,D5,D6,D7,CS);

input [2:0] A;//定义输入信号
wire [2:0] A;//定义内部结点信号数据类型
input D0;
input D1;
input D2;
input D3;
input D4;
input D5;
input D6;
input D7;
input CS;
wire CS;
output DOUT;//定义输出信号
reg DOUT;
always @(CS or D0 or D1 or D2 or D3 or D4 or D5 or D6 or D7) //过程块结构，以下是逻辑功能描述部分
begin
if (CS==1)
DOUT<=0;
else
case(A) //输入，输出对应的情况，即为行为描述语句
3'b000 : DOUT = D0;
3'b001 : DOUT = D1;
3'b010 : DOUT = D2;
3'b011 : DOUT = D3;
3'b100 : DOUT = D4;
3'b101 : DOUT = D5;
3'b110 : DOUT = D6;
3'b111 : DOUT = D7;
default : DOUT = 1;
endcase
end
endmodule

LIBRARY IEEE
USE IEEE.STD_LOGIC_1164.ALL
ENTITY mux81 IS
PORT (s1, s2 : IN STD_LOGIC;
a0,a1,a2,a3,a4,a5,a6,a7,a8 : IN STD_LOGIC;
z : OUT STD_LOGIC);
END ENTITY mux81
ARCHITECTURE activ OF mux81 IS
SIGNAL s : STD_LOGIC_VECTOR (2 DOWNTO 0);
BEGIN
s <= s0 & s1 & s2 ;
PROCESS (s , a0, a1, a2, a3, a4, a5, a6, a7,) –-注意这里必须以s 为敏感信号而非s0、s1 和s2
BEGIN
CASE s IS
WHEN "000" => z<= a0 ;
WHEN "001" => z<= a1 ;
WHEN "010" => z<= a2 ;
WHEN "011" => z<= a3 ;
WHEN "100" => z<= a4 ;
WHEN "101" => z<= a5 ;
WHEN "110" => z<= a6 ;
WHEN "111" => z<= a7 ;
WHEN OTHERS => z<= 'X' ;--注意这里的X 必须大写
END CASE
END PROCESS
End activ

library ieee；
use ieee.std_logic_1164.all；
entity choose8to1 is
port()
哎呀
很简单啦
我有事
下次再帮你拉